This invention concerns a semiconductor device and a method of manufacturing the semiconductor device.
In the field of semiconductor devices, reduction in the size and increase in the speed of semiconductor device have been demanded. Semiconductor devices that can reduce the size and increase the speed include, for example, those described in Japanese Unexamined Patent Publication No. 2011-54920.
The semiconductor device described in Japanese Unexamined Patent Publication No. 2011-54920 has a hybrid circuit in which a logic circuit and a memory circuit are hybridized on one identical substrate. Capacitance devices forming a memory circuit are buried in a layer common with a multilayered wiring layer forming a logic circuit. An upper interconnect layer is formed over the capacitance devices. The interconnect of the upper interconnect layer (fifth layer interconnect 55) is utilized as a word line backing interconnect (column 0123 in Japanese Unexamined Patent Publication No. 2011-549920). The word line backing interconnect decreases the resistance of a word line.
Further, Japanese Unexamined Patent Publication No. 2009-105149 describes a semiconductor device in which bit lines are disposed in a layer over the capacitance devices. The bit line is coupled electrically by way of a contact with a diffusion layer of a transistor. The contact is disposed between each of the capacitance devices in adjacent to them.